A semiconductor storage device (memory) is known in which a resistive storage element whose resistance value is changed based on its state is used as a memory cell. The magnetoresistive element and the phase-change resistive element are known as the resistive storage elements. The magnetoresistive element indicates a magnetoresistance effect such as an AMR (Anisotropic MagnetoResistance) effect, a GMR (Giant MagnetoReistance) effect and a TMR (Tunnel MagnetoResistance) effect. The phase-change resistive element uses a difference between crystalline properties caused by cooling speeds.
At first, as one example of the magnetoresistive element, the TMR element will be described. The TMR element has the structure in which a tunnel insulating film is put between two magnetic materials. FIG. 1 is a sectional view showing one example of the TMR element, which is disclosed in 2000 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS (p. 128). The TMR element (magnetoresistive element) 205 has a structure in which an antiferromagnetic layer 201, a pinned layer 202, a tunnel insulating layer 203 and a free layer 204 are laminated in this order. The antiferromagnetic layer 201 is made of, for example, FeMn (10 nm). The pinned layer 202 is made of, for example, ferromagnetic material CoFe (2.4 nm). The tunnel insulating layer 203 is made of, for example, Al2O3 (2 nm). The free layer 204 is made of, for example, ferromagnetic material NiFe (5 nm). Conductive wirings are connected to the antiferromagnetic layer 201 and the free layer 204 so that voltages can be applied. The magnetization direction of the pinned layer 202 is pinned in a certain direction by the antiferromagnetic layer 201. The free layer 204 is formed to be easily magnetized in a certain direction, and the magnetization direction can be changed when a magnetic field is applied from outside. In the horizontal direction of the free layer 204, a direction in which it is easy to magnetize the free layer 204 is referred to as an easy axis, and a direction which is vertical to the easy axis and in which it is hard to magnetize the free layer 204 is referred to as a hard axis. When the voltage is applied between the free layer 204 and the pinned layer 202, a current flows through the tunnel insulating layer 203. At that time, based on the relation between the direction of the magnetization of the free layer 204 and the direction of the magnetization of the pinned layer 202, the resistance value is changed. That is, when the directions of the magnetizations are the same, the resistance value is low, and when the directions of the magnetizations are opposite, the resistance value is high.
One example of using the TMR element as the storage element of a semiconductor storage device will be described below. FIG. 2 is a perspective view showing one example of a semiconductor storage device, which is disclosed in 2000 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS (p. 130). This nonvolatile memory 215 uses the TMR element as the storage element. In the nonvolatile memory 215, pairs of intersected wirings (bit lines 206 and write word lines 209) are provided on and under TMR elements 205 arranged in an array shape. The bit line 206 is connected to the free layer 204 of the TMR element 205. The write word line 209 is separately provided below the antiferromagnetic layer 201 of the TMR element 205. The antiferromagnetic layer 201 of the TMR element 205 is connected to the drain of a transistor 208 formed in a lower layer through a third wiring 207. The transistor 208 is turned on/off by a read word line 210.
A data is written to this TMR element 205, as follows. Since a current flows through the bit line 206 and the write word line 209, a synthesis magnetic field is generated in the vicinity of the intersection. The synthesis magnetic field changes the direction of the magnetization of the free layer 204 in the TMR element 205 which is located at the intersection. The direction of the magnetization is set by the direction of the current. Consequently, the resistance value of the TMR element 205 can be changed. The data is read from this TMR element 205, as follows. The transistor 208 connected to the TMR element 205 from which the reading is executed is turned on by the read word line 210. Then, a voltage is applied to the TMR element 205 through the bit line 206, and the resistance value of the TMR element 205 is evaluated based on the current flowing through the TMR element 205.
Also, U.S. Pat. No. 6,259,644 discloses a data reading method of a cross point type memory array in which resistive storage elements are used. FIG. 3 is a schematic block diagram describing an equivalent potential reading method (hereafter, referred to as a EP method) disclosed in U.S. Pat. No. 6,259,644. In a cross point type memory array 235, a memory cell 222 (TMR element) is connected between a bit line 220 and a word line 222 that intersect each other. In the EP method, a voltage source 223 applies a voltage Vs to the word line 221 connected to the memory cell 222 from which the reading is executed, and the other word lines are grounded. Moreover, a potential setting circuit 224 is connected to the bit line 220 connected to the memory cell 222 from which the reading is executed, and the other bit lines are grounded. The potential setting circuit 224 is composed of a differential amplifier 225 and a feedback resistor 226. One input of the differential amplifier 225 is grounded, and the other input is connected to the bit line 220. Moreover, the potential of the bit line 220 to which the output of the differential amplifier 225 is connected through the feedback resistor 226 is set at a zero potential. With such setting, the bit line 220 and the word line 221 from which the reading is not executed have the zero potentials. Thus, there is no leakage current from the memory cell 222, from which the reading is not executed, on the bit line from which the reading is executed. Hence, the output potential of the potential setting circuit 224 corresponds to the resistance value of the memory cell 222 from which the reading is executed. When this potential is supplied to a sensing amplifier 227 and compared with a referential potential Vref, the data can be judged.
In this way, as the typical memory array in the semiconductor storage device, there are a 1Tr+1R type (Tr: Transistor, R: Resistive storage element) and a cross point type. Here, in the 1Tr+1R type, a selection transistor (208) is connected for each storage element (TMR element 205), and the writing/reading is controlled in the bit line (206) and the word lines (209, 210) which intersect each other. In the cross point type, the storage element (222) is connected at the intersection between the bit line (220) and the word line (221). In the 1Tr+1R type, when the reading is executed, it is possible to evaluate the resistance value for each storage element, which enables the reading even from the region where a change amount of the resistance value is small. However, since the area of the selection transistor and the area for the connection are required, it is difficult to employ it for making a higher-capacity memory with a hyperfine structure. On the contrary, in the cross point type, the memory cell area can be made small. However, since all of the storage elements are connected in parallel, it is difficult to accurately evaluate the resistance value of one storage element. In order to cope with this difficulty, the EP method is proposed as the effective reading method. According to this method, it is possible to ideally evaluate the resistance value of each storage element as mentioned above.
However, actually, the EP method has a problem that the output is shifted, depending on the wiring resistance. With reference to FIG. 3, in the memory cell 235, 200 μm on a side, the resistance value of the wiring is about 40Ω as an example. When a read voltage Vs is assumed to be 0.5 V and the resistance value of the memory cell 222 is assumed to have the two values of 10 kΩ (tentatively, the data is assumed to be “0”) and 15 kΩ (tentatively, the data is assumed to be “1”), the flowing currents become 50 μA (“0”) and 33 μA (“1”).
When the data is read from the memory cell 222 on the word line 221 that is closest to the potential setting circuit 224 connected to the bit line 220, the read currents are 50 μA ([0]) and 33 μA ([1]), and its difference is 17 μA. However, in the memory cell 222 on the word line 221 that is far away from the potential setting circuit 224, the wiring resistance value of the bit line 220 causes the voltage to be increased by 2 mV. The wiring of the memory cell 220 from which the reading is not executed is grounded. When the 128 word lines 221 are assumed to intersect, the sum of the currents, which leak out to those intersecting wirings, is 13 μA (“0”) and 9 μA (“1”), depending on the data. Thus, the read current is reduced to 37 μA (“0”) and 24 μA (“1”), depending on the data. Thus, as for the read current, the difference between 33 μA of the data “1” in the memory cell 222 in the vicinity of the word line 221 closest to the potential setting circuit 224 and 37 μA of the data “0” in the memory cell 222 in the vicinity of the word line 221 farthest to the potential setting circuit 224 is only 4 μA. In order to make the higher-capacity semiconductor storage device, the memory array 235 is required to be made larger. However, since the wiring length becomes long, the read current difference is further reduced, which makes the reading difficult.
Japanese Laid-Open Patent Application JP-P 2002-170377A (corresponding to U.S. Pat. No. 6,778,430B2) discloses a thin film magnetic storage device. This thin film magnetic storage device includes a memory array having a plurality of magnetic memory cells that are arranged in a matrix shape. Here, each of the plurality of magnetic memory cells includes a storage unit in which a resistance value is changed based on the level of a written storage data, when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field. This further includes a plurality of write word lines, which are installed correspondingly to the rows of the magnetic memory cells, respectively, and constituted by the wirings having a first resistivity. Here, each of the plurality of write word lines is selectively activated in accordance with the row selection result, in both cases of writing the data and reading the data. This further includes: a word line current control circuit for generating and shutting down the current route of the first data write current, respectively, in each of the cases of writing the data and reading the data, for at least one activated write word line among the plurality of write word lines; a plurality of data lines which are arranged correspondingly to the columns of the magnetic memory cells, respectively; a reading writing control circuit for supplying each of the second data write current and data read current to one data line corresponding to the column selected from the plurality of data lines, in each of the cases of writing the data and reading the data; and a plurality of read word lines which are arranged correspondingly to the rows of the magnetic memory cells, respectively, and constituted by the wirings having a second resistivity higher than the first resistivity. Each of the read word lines is selectively activated together with the write word line correspondingly to the row selection result, when the data is read.
Japanese Laid-Open Patent Application JP-P 2002-269968A (corresponding to U.S. Pat. No. 6,614,682B2) discloses an information reproducing method of a ferromagnetic memory. This ferromagnetic memory includes a plurality of units, each of which includes: variable resistors arranged in a matrix shape, a plurality of bit lines parallel to each other, and a plurality of sensing amplifiers connected to the bit lines. The variable resistor is composed of a hard layer that is made of ferromagnetic material and stores an information based on a magnetization direction, anon-magnetic layer, and a soft layer made of a ferromagnetic material whose magnetic coercive force is smaller than the hard layer. In order to parallel output a plurality of information at the same time, the plurality of sensing amplifiers in the unit is activated at the same time, the plurality of units are sequentially switched in synchronization with a clock pulse and the sensing amplifiers in the plurality of units are activated, the information are parallel outputted from the plurality of sensing amplifiers in the plurality of units in synchronization with the clock pulse. Thus, the information is continuously reproduced.
Japanese Laid-Open Patent Application JP-P 2003-7982A (corresponding to U.S. Pat. No. 6,683,802B2) discloses a magnetic storage device and a designing method of a magnetic storage device. This magnetic storage device includes a plurality of first wirings extended in a first direction; a plurality of second wirings extended in a second direction different from the first direction; and magnetic elements which are placed at the intersections between the first wirings and the second wirings and include at least ferromagnetic films whose magnetization directions are variable. In the magnetic storage device, the synthesis magnetic field generated by the currents that flow through the selected first wiring and second wiring is used to change the magnetization state of the predetermined magnetic element arranged at the intersection between the wirings and consequently write the information. In at least one combination of: a combination in which a distance between the first wiring and the predetermined magnetic element at the intersection to which the information is written is d, a magnitude ratio of the second direction component of the synthesis magnetic field in the adjacent magnetic element in the second direction to the predetermined magnetic field is γ, and an interval between the predetermined magnetic element and the adjacent magnetic element is p; and a combination in which a distance between the second wiring and the predetermined magnetic element at the intersection is d, a magnitude ratio of the first direction component of the synthesis magnetic field in the adjacent magnetic element in the first direction to the predetermined magnetic element is γ, and an interval between the predetermined magnetic element and the adjacent magnetic element is p, this is set such that the d satisfies the relation of d≦p×(γ/(1−γ))·1/2 (here, 0<γ<1).
Japanese Laid-Open Patent Application JP-P 2003-318370A (corresponding to U.S. Pat. No. 6,912,152B2) discloses a magnetic random access memory. This magnetic random access memory includes: a memory cell array having a plurality of memory cells in which a magnetic resistance effect is used; a first function line that is extended in a first direction inside the memory cell array and commonly connected to one ends of the plurality of memory cells; a plurality of second function lines that are arranged correspondingly to the plurality of memory cells and extended in a second direction intersecting the first direction inside the memory cell array; and a third function line that is separated from the plurality of memory cells and shared by the plurality of memory cells. In each of the plurality of memory cells, the other end is independently connected to one of the plurality of second function lines.
Japanese Laid-Open Patent Application JP-P 2004-206796A (corresponding to U.S. Pat. No. 6,961,261B2) discloses a magnetic random access memory and a data reading method of the magnetic random access memory. In this magnetic random access memory, one block is configured by a plurality of magnetoresistive-effect elements in which a magnetoresistive effect is used to store a data, and this block includes a plurality of memory cell arrays that are arranged in a row direction and a column direction. This includes: a plurality of first magnetoresistive-effect elements placed inside a first block; a plurality of first word lines that are respectively independently connected to one ends of the plurality of first magnetoresistive-effect elements and extended in the row direction; a first read sub bit line that is commonly connected to the other ends of the plurality of first magnetoresistive-effect elements; a first block selection switch in which one end of a current route is connected to the first read sub bit line; and a first read main bit line that is connected to the other end of the current route of the first block selection switch and extended in the column direction.
Japanese Laid-Open Patent Application JP-P 2004-213771A (corresponding to U.S. Pat. No. 6,862,210B2) discloses a magnetic random access memory. This magnetic random access memory includes a memory cell configured by a magnetoresistive element whose electric resistance value is changed by a magnetism; a sub bit line connected to one end of the memory cell; a main bit line connected through a first selecting circuit to the sub bit line; a sensing amplifier connected through a second selecting circuit to the main bit line; a wiring that is connected to the other end of the memory cell and arranged in a first direction; a first operation circuit connected through a third selecting circuit to one end of the wiring; a second operation circuit connected to the other end of the wiring; and a word line that passes above an intersection at which the memory cell and the wiring are connected and is arranged in a second direction orthogonal to the first direction. At a time of a reading operation for reading a data from the memory cell, the first operation circuit functions as a word line driver, and the wiring serves as the word line for reading. At a time of a writing operation for writing the data to the memory cell, the first and second operation circuits function as one of a bit line driver and a bit line sinker circuit, and the wiring serves as the bit line for writing.
Japanese Laid-Open Patent Application JP-P 2005-101535A (corresponding to U.S. Patent Application US2005045919A1) discloses a semiconductor device. This semiconductor device includes: first and second wiring layers different from each other; and a via connecting a wiring in the first wiring layer and a wiring in the second wiring layer and including a member whose conductivity is variable. The via functions as a switch element of a conductivity-variable type, in which a contact portion between the via and the first wiring is defined as a first terminal, and a contact portion between the via and the second wiring is defined as a second terminal. In the switch element, the connection state between the first terminal and the second terminal can be variably set to a shorted state, an opened state or a middle state between the shorted state and the opened state.
Japanese Laid-Open Patent Application JP-P 2005-182986A (corresponding to U.S. Pat. No. 6,980,465B2) discloses an address specifying circuit for a cross point memory array including a cross point resistance element. This address specifying circuit address-specifies a cross point memory array that has address lines of a first set and address lines of a second set. This includes: cross point resistance elements (114) of the first set connected to the address lines (116) of the first set; cross point resistance elements (114) of the second set connected to the address lines (126) of the second set; and at least one of a pull-up cross point resistance element (112) connected to the address line (116) of the first set and a pull-down cross point resistance element (122) connected to the address line (126) of the second set.
National publication of translated version JP-P 2005-522045A (international Publication WO03085675A2) discloses a phase-change memory device. This phase-change memory device includes: a substrate; a plurality of first wirings parallel to each other that are formed on the substrate; a plurality of second wirings parallel to each other that are formed on the substrate to intersect the first wirings while insulated from the first wirings; and memory cells which are arranged at respective intersections between the first wirings and the second wirings and in which one ends are connected to the first wirings and the other ends are connected to the second wirings. The memory cell includes: a variable resistance element for storing a resistance value, which is determined by a phase change between a crystal state and an amorphous state, as an information; and a Schottky diode connected in series to this variable resistance element.